• Develop and implement system-level models for complex PLLs and their sub-blocks.
• Contribute to the definition of system architectures and partition design specifications between analog and digital domains.
• Assist in creating comprehensive verification plans for mixed-signal designs, including corner case analysis and performance characterization.
• Develop and execute verification test benches and scripts using industry-standard tools and methodologies.
• Analyze simulation results, identify discrepancies, and debug design issues in collaboration with analog and digital design teams.
• Support the integration of analog and digital blocks at the top level of the IC.
• Contribute to technical documentation and design reviews.
• Continuously learn about PLL architectures, mixed-signal design principles, and advanced verification techniques.

• Bachelor's degree in Electrical Engineering.
• 0-2 years of experience in IC design, verification, or system-level modeling (through internships, academic projects, or early professional roles).
• Solid understanding of fundamental electrical engineering principles and digital circuit design.
• Familiarity with mixed-signal concepts and the interaction between analog and digital blocks.
• Basic knowledge of Verilog, SystemVerilog, or Verilog-A/AMS for modeling and verification.
• PLL System-Level design experience is highly appreciated
• Experience with AMS simulation tools is a plus.
• Strong analytical and problem-solving skills with a keen eye for detail.
• Excellent communication and teamwork abilities.
• A strong desire to learn and grow in the field of mixed-signal IC design and verification.

For interested applicants, please send your resume to hr.eg@pearlsemi.com mentioning the Job Code in the subject of the email.

Pearl Semiconductor offers a competitive financial package along with a medical insurance plan that covers the employee and his/her immediate family members.

Pearl Semiconductor is an Equal Opportunity Employer.