• Lead the design, simulation, and layout supervision of high-performance analog building blocks for advanced PLL architectures.
• Contribute to the architectural definition and system-level modeling of innovative PLL designs.
• Conduct comprehensive pre-layout and post-layout simulations to ensure design robustness and meet stringent performance targets (noise, jitter, power, linearity).
• Collaborate closely with digital designers, verification engineers, and test engineers to ensure seamless integration and successful product delivery.
• Drive design reviews and contribute to technical documentation.
• Mentor junior engineers and contribute to a culture of knowledge sharing and technical growth.
• Stay abreast of the latest industry trends, design methodologies, and process technologies relevant to high-performance analog and mixed-signal design.

• Master's or Ph.D. in Electrical Engineering.
• 5+ years of hands-on experience in analog/mixed-signal IC design, with a strong emphasis on high-performance PLLs or their critical analog sub-blocks.
• Deep understanding of PLL architectures (analog, digital, hybrid), theory of operation, and performance metrics.
• Proven expertise in designing key analog building blocks.
• Proficiency with industry-standard EDA tools.
• Experience with layout considerations for high-speed, low-noise analog circuits.
• Excellent problem-solving skills, attention to detail, and a results-oriented approach.
• Strong communication and interpersonal skills, with the ability to collaborate effectively within a multidisciplinary team.
• Familiarity with AMS Behavioral modeling is a plus.

For interested applicants, please send your resume to hr.eg@pearlsemi.com mentioning the Job Code in the subject of the email.

Pearl Semiconductor offers a competitive financial package along with a medical insurance plan that covers the employee and his/her immediate family members.

Pearl Semiconductor is an Equal Opportunity Employer.