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Physical Design & Layout Manager

Pearl Semiconductor

Pearl Semiconductor

Design
Cairo, Cairo Governorate, Egypt
Posted on Aug 1, 2025

Physical Design & Layout Manager

Job Code: EG_PDM_7/25
Location: Cairo, Egypt
Employment Type: Full Time

Responsibilities:

  • Leading, mentoring, and growing a team of skilled layout engineers, fostering a collaborative and high-performance environment.
  • Taking ownership of the physical design execution for complex, high-performance mixed-signal ICs, with a strong focus on PLLs and their critical analog blocks.
  • Defining and implementing layout methodologies and best practices to ensure optimal performance (noise, matching, parasitic control), density, and manufacturability for advanced process nodes.
  • Collaborating closely with analog and digital design teams from architecture definition through tape-out to understand design requirements and translate them into robust physical layouts.
  • Driving layout reviews and ensuring adherence to design rules (DRC), layout versus schematic (LVS), and other verification checks.
  • Developing and maintaining layout automation scripts and methodologies to improve efficiency and reduce cycle time.
  • Acting as a technical expert and problem-solver for complex layout challenges, especially those related to noise isolation, precise matching, and signal integrity in mixed-signal environments.
  • Managing project timelines and resources for layout tasks to ensure on-time delivery.
  • Staying ahead of industry trends in layout tools, process technologies, and methodologies.

Qualifications:

  • Bachelor's degree in Electrical Engineering; Master's preferred.
  • 15+ years of hands-on experience in IC layout, with a significant portion dedicated to high-performance analog and mixed-signal designs.
  • Proven management experience (2+ years) managing a team of layout engineers, preferably in different sites.
  • Deep expertise in the physical design of PLLs and their critical analog blocks.
  • Mastery of industry-standard EDA tools for layout, physical verification and parasitic extraction.
  • Exceptional understanding of layout effects on circuit performance, including noise coupling, matching, parasitic capacitance/resistance, electromigration, and IR drop.
  • Proficiency in scripting languages (e.g., SKILL, Python, Perl, Tcl) for layout automation and productivity enhancement.
  • Excellent communication, interpersonal, and problem-solving skills.
  • A strong commitment to quality and a meticulous attention to detail.

For interested applicants, please send your resume to hr.eg@pearlsemi.com mentioning the Job Code in the subject of the email.

Pearl Semiconductor offers a competitive financial package along with a medical insurance plan that covers the employee and his/her immediate family members.

Pearl Semiconductor is an Equal Opportunity Employer.